1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor memory device suitable to high integration, which stably operates with low power consumption. The present invention relates more specifically to a configuration of a power source for transmitting operating source voltages including a high voltage and a configuration of a voltage generating circuit.
2. Description of the Related Art
FIG. 71 is a diagram showing a configuration of an inverter which is a typical gate circuit. In FIG. 71, the inverter includes a p channel NOS (insulated gate type field effect) transistor PQ connected between a source node 1 and an output node 2, and an n channel MOS transistor NQ connected between the output node 2 and a ground node 3. An input node 4 is connected to the gates of the transistors PQ and NQ. The operation of the inverter shown in FIG. 71 will now be described in brief.
When an input signal IN is high in level, the p channel MOS transistor PQ is turned off and the n channel MOS transistor NQ is turned on. The output node 2 is discharged to a ground potential level through the n channel MOS transistor NQ which is in an on state. When an output signal OUT at the output node 2 is lowered to the ground potential level, a source (corresponding to a conduction terminal connected to the ground node 3) of the n channel MOS transistor NQ becomes equal in potential to a drain (corresponding to a conduction terminal electrically connected to the output node 2) thereof. As a result, no current flows through the n channel MOS transistor NQ.
On the other hand, when the input signal IN is low in level, the n channel MOS transistor NQ is turned off and the p channel MOS transistor PQ is turned on. The output node 2 is charged to-a power source voltage Vcc level through the p channel MOS transistor PQ which is in an on state. When the output signal OUT at the output node 2 is raised to the power source voltage level, the source (corresponding to a conduction terminal connected to power source terminal 1) of the p channel MOS transistor PQ becomes equal in potential to the drain (corresponding to a conduction terminal connected to the output node 2) thereof, so that no current flows through the p channel MOS transistor PQ.
When the output signal OUT makes a transition to a high level or to a low level in the case of a CMOS (Complementary MOS) inverter using the p channel MOS transistor PQ and the n channel MOS transistor NQ, the transistors PQ and NQ are both brought into an off state eventually. As a result, no current consumption is produced in most Pasae. When the output signal OUT changes from the low level to the high level or vice versa, a through-current flows from the power source node 1 to the ground node 3 through the transistors PQ and NQ. Thus, the amount of current consumed can be reduced by using the inverter having the CMOS configuration shown in FIG. 71.
A drain current Ids, which flows through an MOS transistor, is represented as a function of a gate-to-source voltage of the MOS transistor. As the absolute value of the gate-to-source voltage is made greater than that of a threshold voltage of the MOS transistor, the drain current increases. Even when the absolute value of the gate-to-source voltage is less than or equal to that of the threshold voltage, the drain current Ids is not completely brought to 0. The drain current that flows in a gate-to-source voltage region, is called "sub-threshold currents", and is exponentially proportional to the gate-to-source voltage.
FIG. 72 is a graph showing a sub-threshold current characteristic of an n channel MOS transistor. In FIG. 72, the axis of abscissas represents a gate-to-source voltage Vgs and the axis of ordinates represents a logarithmic value of a drain current Ids. Linear regions of curves A and B shown in FIG. 72 represent sub-threshold current regions. In the sub-threshold current regions, a gate-to-source voltage causing a drain current flow of 10 mA through a MOS transistor whose gate width (channel width) is 10 .mu.m, for example, is defined as a threshold voltage. A threshold voltage Vth of a transistor having a sub-threshold current characteristic of the curve A is shown in FIG. 72. As is seen from FIG. 72, a sub-threshold current It flows even when the gate-to-source voltage Vgs of the MOS transistor is 0V. When the number of MOS transistors used as components increases in a large scale integrated circuit device, the sum of values of sub-threshold currents attains a non-negligible, thereby causing a problem that the current consumption increases.
On the other hand, in a large scale integrated circuit device such as a large storage capacity semiconductor memory device or the like, an operating power source voltage Vcc tends to be set to a low voltage of 1.5V, for example, for the purpose of reducing power dessipation, speeding up its operation owing to a reduction in the amplitude of a signal and using a battery power. When the power source voltage Vcc is lowered, it is necessary to scale down a MOS transistor depending on the power source voltage in accordance with a scaling rule. When the MOS transistor is scaled down, it is also necessary to lower the threshold voltage Vth proportionally (when an n channel MOS transistor is used). However, the threshold voltage cannot be lowered in accordance with the scaling rule.
Namely, when the threshold voltage Vth of the MOS transistor having the sub-threshold current characteristic indicated by the curve A is reduced as shown in FIG. 72, the sub-threshold current characteristic represented by the curve A changes into that represented by the curve B. In this case, a problem arises that the sub-threshold current It when the gate-to-source voltage Vgs is 0V is increased to Ita, thereby causing an increase in consumed current.
Further, a high voltage Vpp greater than the operating source voltage Vcc is employed in a semiconductor memory device. By making use of the high voltage Vpp, the influence of a signal voltage loss produced by a threshold voltage of a MOS transistor is prevented and a signal having a power source voltage Vcc level is transmitted. Portions using such a high voltage Vpp will be described in detail later. However, a word driver for driving a word line into a selected state, for example, uses Vpp in the semiconductor memory device.
When the high voltage Vpp is used, the high voltage Vpp is applied in place of the source voltage Vcc in FIG. 71. When the input signal IN is at a high voltage Vpp level, the p channel MOS transistor PQ is turned off. At this time, the n channel MOS transistor NQ is turned on and hence the output node 2 is discharged to the ground potential level. Since the high voltage Vpp is applied between the source and drain of the p channel MOS transistor PQ in this case, the voltage applied therebetween is made greater than the operating source voltage Vcc even if the gate-to-source voltage Vgs is 0V, whereby an electric charge is accelerated and more current flows so as to increase a sub-threshold current. Namely, the curve A shown in FIG. 72 changes into the curve B thereby to increase the sub-threshold currents When the threshold voltage is determined, a drain voltage is set to a predetermined value. When the threshold voltage is reduced under the same drain voltage, the sub-threshold current increases. However, even if the MOS transistor has the same threshold voltage, if the drain voltage increases, then the curve A changes into the curve B.
The sub-threshold current characteristic of the p channel MOS transistor is represented by reversing the sign of the gate-to-source voltage Vgs of the curve shown in FIG. 72.
In the circuit operating with the internal voltage such as the operating source voltage Vcc or the high voltage Vpp as described above, it is necessary to reduce a leakage current (sub-threshold current) of MOS transistor operating in the sub-threshold current region as small as possible.
FIG. 73 is a diagram showing one example of a conventional power source arrangement for reducing the sub-threshold current. In FIG. 73, the power source arrangement includes a main power source voltage transmission line (hereinafter called simply "main source line") 10 connected to a source voltage supply node 11, a sub source voltage transmission line (hereinafter called "sub source line") 12 supplied with a power source voltage VC from the main source line 10, a switching transistor SW1 composed of a p channel MOS transistor, which is connected between the main source line 10 and the sub source line 12 and electrically connects the main source line 10 and the sub source line 12 to each other in response to a control signal .phi.CT, and a current control circuit 15 provided between the main source line 10 and the sub source line 12. The current control circuit 15 is composed of an n channel MOS transistor 16 whose drain and gate are connected to the main source line 10 and whose source is connected to the sub source line 12. The n channel MOS transistor 16 serves as a diode and has a function of clamping the voltage on the sub source line 12 to VC-VT level. Here, VT represents a threshold voltage of the n channel MOS transistor 16.
Gate circuits G1 and G2 are connected between the sub source line 12 and other power source voltage transmission line (hereinafter called "ground line") 3. The number of the gate circuits is arbitrary. However, two gate circuits are typically illustrated in FIG. 73. The gate circuits G1 and G2 each have a configuration of a CMOS inverters. The gate circuits G1 and G2 respectively operates with voltage VC on the sub source line 12 and a ground voltage Vss on the ground line 3 both as operating source voltages so as to invert signals IN1 and IN2 supplied thereto and output signals OUT1 and OUT2 therefrom. The operation of the power source arrangement will now be described in brief with reference to FIG. 74.
When the gate circuits G1 and G2 are on standby (in a waiting state), the control signal .phi.CT is at a high level corresponding to source voltage VCH level. At this time, the gate and drain of the switching transistor SW1 become identical in potential to each other and it is hence brought into an off state. When the voltage VC on the sub source line 12 is reduced owing to a leakage current, a current is supplied from the n channel MOS transistor 16 so that the voltage on the sub source line 12 is maintained at VC-VT level. When the input signal IN1 is at a high level corresponding to source voltage VC level upon standby of the gate circuit G1, a p channel MOS transistor PQ is turned off and an n channel MOS transistor NQ is turned on. Hence the output signal OUT1 is brought to ground voltage Vss level. At this time, the voltage VC applied to the source of the p channel MOS transistor PQ is lower than the voltage applied to the gate thereof so that the p channel MOS transistor PQ is brought into a deeper off state, thereby making it possible to suppress a sub-threshold current that flows through the p channel MOS transistor PQ. The input signal IN2 is also at a high level and hence the output signal OUT2 is low in level.
When the gate circuits enter into an operating cycle, the control signal .phi.CT is brought to a low level corresponding to the ground voltage Vss level so that the switching transistor SW1 is turned on. Consequently, the sub source line 12 and the main source line 10 are electrically connected to one another to reset the voltage VC on the sub source line 12 to the source voltage VCH level (time T1). After the voltage VC on the sub source line 12 has been reset to the predetermined source voltage VCH level and settled, the input signal IN1 is reduced to the low level corresponding to the ground voltage level at a time T2 so that the output signal OUT1 is raised to a high level. During the operating cycle, the voltage VC on the sub source line 12 is identical in level to the voltage VCH on the main source line 10 and the n channel MOS transistor 16 is in an off state.
When the operating cycle is completed at a time T3, the control signal .phi.CT is raised to the high level again to turn off the switching transistor SW1. Even if the voltage VC on the sub source line 12 is reduced due to a leakage current (including a sub-threshold current that flows through each of the gate circuits G1 and G2), when the voltage VC on the sub source line 12 is reduced to VCH-VT level or less, the n channel MOS transistor 16 is turned on so as to supply the current to the sub source line 12, so that the voltage VC on the sub source line 12 is maintained at the VCH--VT voltage level.
By arranging source lines into a hierarchical structure comprised of a main source line and a sub source line, a MOS transistor brought into an off state can be brought into a deeper off state so that a sub-threshold current can be reduced. With a decrease in the power source voltage, a MOS transistor having a threshold voltage reduced in accordance with a scaling rule can be used, thereby making it possible to ensure a high-speed operation using a low voltage power source.
However, when a diode-connected clamp transistor is used, voltage VC on the sub source line is reduced in level by a threshold voltage VT of the clamp transistor with reference to source voltage VCH. Even if the threshold voltage of a MOS transistor having a threshold voltage ranging from 0.8V to 1.0V for the power source voltage of 5V is reduced to a level within 0.25V to 0.3V for the power source voltage of 1.5V in accordance with the scaling rule and the MOS transistor having such a low threshold voltage is used, in a time interval T1-T0 shown in FIG. 74 it is required to restore the voltage vC on the sub source line 12 to the source voltage VCH level. The gate circuits G1 and G2 and the like are operated at a time T2 after the voltage VC on the sub source line 12 has been recovered and settled to the source voltage VCH level. Thus, a problem arises that operation start timing of each of the gate circuits G1 and G2 cannot be made earlier and when the semiconductor integrated circuit device is a semiconductor memory device, access times are made long and high-speed operation characteristics seen from the outside are impaired.
In the power source arrangement shown in FIG. 73, the input signals IN1 and IN2 are high in level upon standby. It is also necessary to determine a logic level of each input signal in advance. In a statically-operating circuit or the like, a voltage level of a signal inputted thereto during a standby cycle is unpredictable. Accordingly, the conventional power source arrangement has a drawback that the arrangement is merely applicable to a device that is able to predict the logic level of an input signal.
Further, when a semiconductor memory device is used, a substrate bias voltage that is a negative voltage Vbb, is generally applied to a substrate region (substrate or well region) for the purpose of, for example, reducing junction capacitance, preventing a parasitic MOS transistor from occurring and stabilizing a threshold voltage of a MOS transistor. The high voltage Vpp and the negative voltage Vbb are both generated by a charge pump operation of a capacitor based on the voltages VC and Vss. A low power source voltage configuration is required to efficiently generate a high voltage Vpp at a high voltage level and a negative voltage Vbb at a low voltage level. It is also necessary to provide a power source arrangement that is able to make power consumed by a circuit for generating the high voltage Vpp and the negative voltage Vbb as low as possible.